Modern electronic systems are often very large and complex, and may be built from tens or even hundreds of millions of transistors, making these systems difficult and expensive to design and validate. Market demands may require systems to possess ever-increasing performance, advanced feature sets, system versatility, and a variety of other rapidly changing system specifications. These demands often introduce contradictory design requirements into the design process. System designers are required to make significant tradeoffs in performance, physical size, architectural complexity, power consumption, heat dissipation, fabrication complexity, and cost, among others, to try to best meet design requirements. Each design decision exercises a profound influence on the resulting electronic system. To handle such electronic system complexity, designers create specifications and design electronic systems around the specifications. The specifications attempt to balance the many disparate demands being made of the electronic systems and contain the exploding design complexity.
The process of comparing proposed designs to the specifications around which they were constructed helps ensure that the designs meet critical system objectives. The process of comparison is called verification. Logic systems may be described at a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. Most designers describe and design their electronic systems at a high-level of abstraction using an IEEE Standard hardware description language (HDL) such as Verilog™, SystemVerilog™, or VHDL™. Often, a high-level HDL is easier for designers to understand, especially for a vast system, as the high-level HDL may describe highly complex concepts that are difficult to grasp using a lower level of abstraction. A HDL description may be converted into another, lower level of abstraction if helpful to the developers. For example, a high-level description may be converted to a logic-level description such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. Each lower level of abstraction introduces more detail into the design description.
Many of the steps in a design automation chain may be performed using a correct-by-construction model. The lower-levels of abstraction may be generated automatically by computer, derived from a design library, or created by another design automation technique. For example, the generation of a gate-level description from a logic-level description can be easily verified for equivalence due to a one-to-one correspondence between a construct in the RTL and a set of gates in the gate-level description. But other steps may be more difficult to verify. In some cases, a section of the design may be manually constructed to optimize for certain parameters, and two different abstractions of the design may not share a one-to-one correspondence. In other cases, the design complexity may preclude easy verification, using the automated tool, that the design's output is equivalent to the design's input. Ultimately, it is critical to ensure that the performance of any produced lower-level designs still matches the requirements of the system specification and still provides the desired logic function.